emacs. verilog mode guide, example

//Shift Enter 普通换行Cmd callingcommand! -bar V execute !emacs --no-site-file -l $AQARCH/tools/elisp/verilog-mode-init.el --batch . bufname(%) . -f verilog-auto -f save-buffercommand! -bar VR execute !emacs --no-site-file -l $AQARCH/tools/elisp/verilog-mode-init.el --batch . bufname(%) . -f verilog-batch-delete-auto -f save-buffernnoremap silent \p :execute normal! . mA;. CRcommand! -bar VSY execute !emacs --no-site-file -l ~/scfile/my_module.el -l $AQARCH/tools/elisp/verilog-mode-init.el --batch . bufname(%) . -f verilog-auto -f delete-dup-lines-separately -f save-buffer inoremap \s EscmA;Esccommand! -bar MV execute !emacs --no-site-file -l /workspace/IPDHW01/apolloz/project/apolloz_isp9000_090424/project.isp/arch/XAQ2/tools/elisp/verilog-mode-init.el --batch . bufname(%) . -f verilog-auto -f save-buffercommand! -bar MVR execute !emacs --no-site-file -l /workspace/IPDHW01/apolloz/project/apolloz_isp9000_090424/project.isp/arch/XAQ2/tools/elisp/verilog-mode-init.el --batch . bufname(%) . -f verilog-batch-delete-auto -f save-bufferusage/*CAM_SYS_NOC AUTO_TEMPLATE (//vi200 axi signals.m\(14\|15\|16\|17\)_vi200_\(.*\)_awaddr ( {m\1_vi200_\2_awaddr[39:4],4d0} ),.m\(14\|15\|16\|17\)_vi200_\(.*\)_awuser ( {12d0,m\1_vi200_\2_awuser[3:0]} ),//s0_ddr signal.s0_ddr_wid ( ),.s\(2\|3\|4\)_\(.*\) ((if (equal vl-dir \\output\\) \\\\ (concat vl-width \\b0\\))),.out_\(.*\) ((if (equal vl-dir \\output\\) \\\\ (concat vl-width \\b0\\))),//mode: Verilog//verilog-auto-output-ignore-regexp://\\(vi200_pixel_ctrl\\|slcr_xbar.*_sel\\|pready_.*\\|prdata_.*\\|apm_.*\\|paddr_mi\\|csi.*_phy_.*_TXBITCLK\\|rxwordclkhs_test_out\\|scan_clk_gate_out\\|slcr_vi200_axi_high_addr\\|.*DIG_TEST\\)//verilog-library-directories: (. /ux/Nuclei_Vpi_SOC/users/zjxiao/nuclei_vpi_de/asic/rtl/csi_sys/rtl_v/csi_wrapper/ /home/reltp/IP/VS_IPD_from2011/Verisilicon_HW_vi200_2_2_0_rc0f_obf_0x500000D5_20250121/Vivante_vi200_hardware_2_2_0_rc0f_obf/rtl/vi200 /home/reltp/IP/VS_IPD_from2011/Verisilicon_HW_DW200_5_2_0_rc0h_obf_0x500000D6_20250121/Vivante_dw200_hardware_5_2_0_rc0h_obf/rtl/dw200 /ux/Nuclei_Vpi_SOC/users/zjxiao/nuclei_vpi_de/asic/rtl/blocks/vsi_apb_bridge/rtl_v /ux/Verisilicon_IP/IPD/Verisilicon_HW_isp8000_8_5_0_rc0c_obf_0x500000F4_20250905/Vivante_isp8000_hardware_8_5_0_rc0c_obf/rtl/isp8000 /ux/Nuclei_Vpi_SOC/users/zjxiao/nuclei_vpi_de/asic/rtl/blocks/vsi_apb2ahb/rtl /ux/Nuclei_Vpi_SOC/users/zjxiao/nuclei_vpi_de/asic/rtl/blocks/vs_axi_perf_mon/rtl ./crm_new)//verilog-auto-inst-param-value: t//verilog-library-extensions:(.v .h)//verilog-library-flags:(-f ./input.vc -v /path/to/specific_file.v)//verilog-library-files:(/workspace/IPDHW01/apolloz/isp_pipe_div.v)//End:/*sysram AUTO_TEMPLATE(.axi_npu_\(.*\)((upcase \\\1\\)_DDR),.axi_npu_bid (BID_DDR[3:0]), //TODO.axi_m4_int_\(\(ar\|r\).*\)(axi_rd2_int_\1_[]),);*/ for inst number/* InstModule AUTO_TEMPLATE \_\\([a-z]\\)\ (.ptl_mapvalidx (_ptl_mapvalid),.ptl_mapvalidp1x (ptl_mapvalid_),);*/